During manufacturing test, debug and diagnosis of an integrated circuit, visibility into the internal state of the integrated circuit is often needed. Defects in the fabricated circuit may manifest themselves as erroneous states in flip-flops which may or may not be propagated to the integrated circuit pins or pads during testing.
Two general categories of testing may be employed to test the integrated circuit. The first category of testing may be referred to as functional testing. Functional testing may be utilized to verify correct circuit operation according to its functional specification. The second category of testing may be referred to as structural testing. Structural testing may use structural test patterns that may have no notion of circuit functionality (e.g., whether a floating point unit, branch prediction unit, memory interface, etc., is being tested). As such, structural testing makes no direct attempt to determine if the overall functionality of the circuit is correct. Rather, structural testing typically relies on a structural netlist to verify that the circuit has been assembled correctly from low-level building blocks.
Generally, the efficiency of test and debug is dependent on the level of observability into the internal state of the integrated circuit. Propagation of internal faults to the pins or pads of an integrated circuit may be difficult because: 1) the available automatic test equipment memory may be insufficient to hold the expected responses when stored as one bit per pin per clock cycle; 2) propagation of an internal fault to an I/O pin may become increasingly difficult as the ratio of flip flops to I/O pins increases; 3) association of an observed failure at an I/O pin with the proper internal clock cycle may become increasingly difficult as internal clock frequencies continue to increase relative to I/O clock frequencies; and/or 4) automatic test equipment may not be able to strobe output pins with plesiochronous interfaces that do not behave deterministically with respect to a reference clock.
During manufacturing test, debug and diagnosis of an integrated circuit, the integrated circuit generally undergoes testing to verify proper operation, detect failures and isolate faults. As mentioned above, two general categories of testing may be employed to test the integrated circuit, including functional testing and structural testing. Functional testing may be utilized to verify correct circuit operation according to its functional specification. Functional testing may execute functional code at speed (e.g., instruction codes for a microprocessor). Functional testing may also be used to perform speed binning, i.e., sorting a device according to operating speed range (e.g., 3 GHz, 3.5 GHz, 4 GHz, etc).
As introduced above, structural testing may use structural test patterns that may have no notion of circuit functionality (e.g., whether a floating point unit, branch prediction unit, memory interface, etc., is being tested). Structural testing typically relies on a structural netlist to verify that the circuit has been assembled correctly from low-level building blocks. For example, structural testing may be performed to verify that all specified logic gates are present, that each gate is operational, and that the gates are correctly interconnected. Structural testing is generally more efficient at targeting certain types of defects, but may not be suitable for detecting certain types of functional or at speed defects that may occur when a complex device such as a microprocessor is tested.
Structural testing generally may make use of extra circuitry added to the integrated circuit to aid testing. For example, during integrated circuit design, extra circuitry may be included on the chip to interconnect flip flops into a scan chain. Such a scan chain may be used to shift in test patterns to drive combinatorial logic. Once the pattern has been shifted in, a functional clock signal may be applied to the circuit and the results of the combinatorial logic evaluation may be captured in the scan chain flip-flops. These results may be shifted out by switching to scan mode and clocking the scan chain to serially shift out the test results.
While structural testing has become more popular due to its cost effectiveness and improved observability of faults, functional testing may still be necessary for speed binning and functional debug/diagnosis. However, as the number of logic functions included on integrated circuits continues to increase and as the internal clock rate continues to increase, functional testing becomes more difficult to perform.
During functional testing, the internal state of the chip may be inferred from knowledge of its external outputs, which is generally referred to as “observability.” To be detectable, an internal fault generally has to be propagated to a point that is observable by the automatic test equipment (ATE) performing the testing, typically an output pin of the circuit. As the ratio of logic functions to number of integrated circuit pins increases, observability may become an issue because the number of defects is generally proportional to the amount of logic on the chip, while observability is generally proportional to the number of pins. Thus, holding the number of chip pins constant while increasing the amount of logic may result in decreased observability of faults (i.e., it may become more difficult to propagate a fault to an output pin).
A second issue with functional testing is that functional testing is generally performed on a cycle-by-cycle basis. A typical ATE applies test vectors to the input pins of the chip and reads results at output pins. Such an ATE generally requires a significant amount of memory, on the order of one bit per pin per test cycle. That is, the number of test vectors necessary to verify proper circuit operation is generally proportional to the amount of logic on the chip. Denser chips generally require more ATE memory to hold the additional test vectors necessary to achieve good test coverage.
A third issue with functional testing is that modern integrated circuits may employ plesiochronous input/output (I/O) pins for chip-to-chip communication. As inter-chip signaling speeds continue to increase, plesiochronous I/O pins continue to become more prevalent. Generally, in a chip-to-chip communication involving plesiochronous pins, the receiving chip has circuitry to interpret the data being received and to synchronize the data to an embedded clock by recovering the clock boundaries. Conventional ATE may not have the necessary circuitry to understand plesiochronous data.
I/O pins may generally be categorized as synchronous (data stream is synchronous with the clock pin), source synchronous (clock signal is forwarded with the data stream and used at the receiving end to synchronize the data) or plesiochronous (clock signal is embedded in the data stream). Synchronous I/O pins may operate at data rates up to 350 MHz while plesiochronous I/O pins may operate at data rates up to 10 GHz. However, conventional functional testers are generally not configured to read plesiochronous I/O pins, as discussed above. Thus, test data generally has to be applied to and be read from synchronous or source synchronous I/O pins. As a result, there may be an increasing discrepancy between the internal clock rate at which the circuit operates during at speed functional testing and the I/O clock rate at which the ATE applies test vectors and reads results. Further, the I/O data rate may be limited by the ability of on-chip drivers to drive the load on the output pin. Output pins generally drive printed circuit board traces while internal nodes are connected on the silicon substrate. Thus, internal nodes generally operate at a much higher clock rate than do I/O pins.
A fourth issue confronting functional testing is that the ATE generally reads data from I/O pins using the appropriate I/O clock to synchronize the data transfer. As a result, the observability of faults propagated to an I/O pin may occur at a much lower data bandwidth than if the faults were internally observed using the internal clock. This may present problems when trying to determine which one of the several internal clock cycles that occur during the I/O clock cycle is the one on which the fault occurred.
Scan based techniques employed during structural testing generally improve observability of faults. For example, a scan mode generally makes all flip-flops of the circuit accessible during testing and allows the flip-flops to be used as a shift register. Thus, a fault only has to be propagated to a flip-flop in the scan chain, rather than out to an I/O pin, to be detectable. FIG. 1 depicts a conventional scan chain 40 that may be used during structural testing of an integrated circuit 38. Scan chain storage elements 10, 12, 14 may be implemented using flip-flops with multiplexed inputs. Each multiplexed flip-flop 10, 12, 14 may include a two-to-one multiplexer 16, 18, 20 and a D-type flip-flop, 22, 24, 26. The multiplexers 16, 18, 20 may allow selection of either normal functional data 28 or scan input data 30. Testing is generally simplified because each multiplexed flip-flop 10, 12, 14 in the integrated circuit may be set and observed during scan mode. The flip-flops may be used to drive inputs of combinatorial logic 32, 34 and to capture outputs of the combinatorial logic 32, 34.
A scan enable signal 36, when asserted, may enable the scan mode, allowing the flip-flops in the integrated circuit 38 to be used as a serial shift register. An input pin or pad 42 may be connected to the input of the first flip-flop 10 of the scan chain 40 to allow data to be serially loaded into the scan chain 40. An output pin or pad 44 may be connected to the output of the final flip-flop 14 of the scan chain 40 to allow test results to be serially shifted out (unloaded). The chip's clock signal 46 may be used to serially load an arbitrary pattern into the scan chain of flip-flops (one bit per clock), and/or to unload the contents of the scan chain 40 (e.g., read out the state of every flip-flop). When the scan mode is selected, for example, via a scan enable pin 48, asserting the scan enable signal 36 may allow the outputs of each storage element in the scan chain 40 to become primary inputs to the combinatorial logic 32, 34, which increases controllability. The inputs of each storage element of the scan chain 40 are generally used to capture outputs of the combinatorial logic 32, 34. Observability increases because a fault only has to be propagated to an input of the scan chain 40, rather than propagated to an I/O pin. Three additional chip pins or pads are generally needed to implement scan testing: the scan input pin 42 for serial data input, the scan output pin 44 for serial data output and the scan enable pin 48 for scan mode control. The scan enable signal 36 may select between the normal functional data input 28, which comes from the combinatorial logic 32, 34, and the scan data 30, which comes from the scan input 42 or the output of the previous flip-flop.
Generally, combinatorial tests may be applied via the scan chain 40. This may be done by asserting the scan enable signal 36 to enter scan mode. Data may be serially loaded into the scan chain 40 from the scan input signal 42 to set up the desired values (e.g., the Q outputs of the flip-flops) to be applied to the inputs of the combinatorial logic 32, 34 (using one scan clock per flip-flop). Then, the scan enable signal 36 may be deactivated to select normal functional mode. The system may then apply one system clock, may apply data at the primary inputs of the chip, and may observe primary outputs of the chip. This may capture data from the combinatorial logic 32, 34 of the circuit in the flip-flops 10, 12, 14 during logic evaluation (e.g., the combinatorial logic outputs connected to the D inputs are transferred to the corresponding Q outputs of the flip-flops). That is, the results are captured and saved in the flip-flops 10, 12, 14. Finally, the scan mode may again be enabled to serially shift out the results of the test. The results may be compared to expected values to determine if the circuit passed the combinatorial test.
The scan chain 40 depicted in FIG. 1 generally uses the same clock 46 to perform scan shifting and logic evaluation. This may be undesirable when performing functional testing and using a scan chain to capture the functional state of the logic circuit. Functional testing may be interrupted (stopped) to shift out the captured state held in the scan chain. The scan chain generally has to be switched to scan mode to serially shift out the results held in the scan chain flip-flops.
What is needed is a mechanism to capture and observe the internal state of an integrated circuit concurrently with functional testing and diagnostics that does not require high-speed pins or plesiochronous pins. Further, what is needed is a way to capture and compress the internal state of the integrated circuit during testing to reduce the amount of automatic test equipment memory needed to run a functional test/diagnostic.